Bandwidth Modelling for Distributed On-Chip RLCG Interconnect Considering Coupling Effects

With the increase in the levels of on-chip integration, the number of functional units integrated onto a single chip is rapidly increasing and as a result, the logic delays are decreasing due to faster transistors. At the same time, the local interconnect delays improve because the physical size of the circuit blocks decrease and the local interconnect spans shorter distances. On the other hand, the global interconnect delay increases with the technology scaling. Multiple design criteria are considered during the interconnect design process, such as delay, power, bandwidth and noise. Performance of any VLSI circuit depends on the bandwidth, as it decreases with the increase in the length of interconnects. Depending on the frequency range of operation, on-chip interconnect can be modelled as lumped and/or distributed RC line for low frequency and as a distributed RLC segments for high frequency. At even higher frequency, of the order of above 10GHz, the shunt conductance needs to be considered for accurate interconnect modelling. In this paper, on-chip interconnect has been modelled as distributed RLCG transmission lines, based on which a crosstalk aware bandwidth estimation method has been proposed in the transform domain in the presence of both inductive as well as capacitive coupling. First, the amount of crosstalk noise that would be induced on the victim line due to the transiting aggressor line has been analytically derived and then from the crosstalk noise voltage, a closed form expression for bandwidth has been proposed for distributed RLCG VLSI interconnects. The calculated bandwidth has been compared with the results obtained from that of SPICE simulation. The simulation shows that the proposed model could result an average error of as low as 15% when compared to the SPICE simulation.