Investigations on Electrical Parameters Degradations of p-GaN HEMTs Under Repetitive UIS Stresses

Electrical parameters degradations of p-GaN high-electron-mobility transistors (HEMTs) under repetitive unclamped-inductive-switching (UIS) stresses have been investigated in this article. With the help of the TCAD simulations, the experimental frequency-dependent conductance analyses ( $G_{p}/\omega$ ), and the experimental capacitance analyses ( $C_{\mathrm {ds}}$ ), it is demonstrated that the trapping effects near the gate region and in the gate to drain access region dominate the degradations. Due to the extremely high-voltage bias during UIS stresses, the trapping of electrons happens near gate region, resulting in the positive shifts of threshold voltage ( $V_{\mathrm {th}}$ ), the degradations of ON-state resistance, the reductions of the gate leakage current, and the reductions of OFF-state leakage current ( $I_{\mathrm {dss}}$ ). Two experimental methods, the $C_{\mathrm {ds}}$ analyses and the $G_{p}/\omega $ analyses, are introduced to characterize the trapping effects in p-GaN HEMT for the first time. Nonetheless, the large current surging during UIS stresses enhances the impact ionization and leads to the increase in $I_{\mathrm {dss}}$ . The analyses above have been validated by the TCAD simulation successfully. For switching parameters, such as the voltage rises/falls time, which should be considered when designing power electronic systems, the increase in $V_{\mathrm {th}}$ induced by the UIS stresses dominates the changes.