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Mapping application performance to HPC architecture

Authors :
A. R. Porter
Charles A. Laughton
L. Steenman-Clark
Christine Kitchen
Lorna Smith
Iain Bethune
Ilian T. Todorov
Eugene E Jones
M. Plummer
B. Ralston
Paul Calleja
Martyn F. Guest
S. Rankin
A. Korzynski
Richard Kenway
Mike Ashworth
Alan Gray
Source :
Computer Physics Communications. 183:520-529
Publication Year :
2012
Publisher :
Elsevier BV, 2012.

Abstract

A suite of application benchmarks, designed to be broadly representative of UK HPC usage, has been developed to stress a broad range of architectural features of large scale parallel HPC resources. A generic methodology to investigate application performance and scaling characteristics has been defined, resulting in a detailed understanding of the performance of these applications. This methodology is transferable to other applications and systems: it is of practical value to developers and users who are aiming for optimal utilisation of HPC resources. An understanding of the performance characteristics of a range of large-scale HPC resources has been obtained using low-level synthetic benchmarks. A relatively simple, qualitative mechanism to assess and predict application performance on current and future architectures using synthetic benchmark results together with application performance analysis results is explored.

Details

ISSN :
00104655
Volume :
183
Database :
OpenAIRE
Journal :
Computer Physics Communications
Accession number :
edsair.doi...........5b1ac19bd1a0516a785bbcd543a661e1
Full Text :
https://doi.org/10.1016/j.cpc.2011.11.013