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Back-gated buried oxide MOSFETs in a high-voltage bipolar technology for bonded oxide/SOI interface characterization
- Source :
- IEEE Electron Device Letters. 19:282-284
- Publication Year :
- 1998
- Publisher :
- Institute of Electrical and Electronics Engineers (IEEE), 1998.
-
Abstract
- A novel back-gated P-MOSFET structure is fabricated in a high-voltage complementary bipolar technology using BESOI (bonded etch back SOI) substrates. The P+ buried layer regions, used for the PNP BJT are used as the source and drain regions, the N- epi as the channel region, the silicon handle wafer as the gate, and the BOX (buried oxide) as the gate oxide. The P-MOSFET was used to characterize the interface between the BOX and the SOI. The devices exhibit high sub-threshold slope which is attributed to a high interface state density of about 2/spl times/10/sup 12//cm/sup 2/ at the bonding interface. Bias-temperature stress measurements show an effective mobile charge density of 4/spl times/10/sup 10//cm/sup 2/ in the buried oxide.
- Subjects :
- Materials science
Silicon
business.industry
Wafer bonding
Bipolar junction transistor
Electrical engineering
Oxide
Silicon on insulator
chemistry.chemical_element
Electronic, Optical and Magnetic Materials
chemistry.chemical_compound
chemistry
Gate oxide
MOSFET
Optoelectronics
Wafer
Electrical and Electronic Engineering
business
Subjects
Details
- ISSN :
- 15580563 and 07413106
- Volume :
- 19
- Database :
- OpenAIRE
- Journal :
- IEEE Electron Device Letters
- Accession number :
- edsair.doi...........592fd57a57f168c7cd48f0c81ce14b6f