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Impact of deep-via plasma etching process on transistor performance in 3D-IC with via-last backside TSV
- Source :
- 2015 IEEE 65th Electronic Components and Technology Conference (ECTC).
- Publication Year :
- 2015
- Publisher :
- IEEE, 2015.
-
Abstract
- 3D-IC (3D-stacked integrated circuit) requires lots of through-Si vias (TSVs) and metal microbumps for electrical connection among stacked LSI chips to realize higher performance beyond 2D-IC. However, plasma etching process for via-last backside TSV formation could damage many transistors used in the 3D-IC. In this study, plasma-induced charge-up damages on transistor characteristics during viahole etching have been investigated using test structures flipchip bonded on Si interposer. Additionally, antenna rules for the 3D-IC layout and process design were also mentioned.
Details
- Database :
- OpenAIRE
- Journal :
- 2015 IEEE 65th Electronic Components and Technology Conference (ECTC)
- Accession number :
- edsair.doi...........58a212ae32758adaeb90e1d341163cf3