Warpage reduction using dielectric layers stress tuning: From analytical model to 3D integration of large die on ceramic substrate

A mechanical study of silicon interposer bow reduction, from wafer level manufacturing to large die stacking including analytical modeling, is presented in this paper. Indeed, understanding and reducing the warpage of a dissymmetrical substrate is fundamental for assembly yield and interconnects reliability. The target here is a bow less than 50 µm for a 650 mm2 Si-interposer.