A software-defined radio FPGA implementation of OFDM-based PHY transceiver for 5G

This paper introduces a software-defined radio implementation of an OFDM-based transceiver for the prototyping and testing of 5G physical layer algorithms. The implementation uses high level abstraction tools to develop and test the algorithms, significantly reducing the time and effort needed to test new features. The proposed architecture adopts interconnecting FIFOs between each functional block, reducing the critical paths and enabling complex designs to be implemented at higher clock rates. The proposed LTE-like transceiver is implemented using COTS FPGA and RF development boards. The real-time over-the-air demonstrator has an on-the-fly scalable bandwidth from 20 to 61.44 MHz, attaining close to 500 Mb/s when using 256-QAM modulation.