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Folded fully depleted Bulk+ technology as a highly W-scaled planar solution

Authors :
Francois Leverd
Jean-Damien Chapon
Remi Beneyton
Stephane Monfray
G. Bidal
E. Deloffre
Stephane Denorme
Mickael Gros-Jean
Thomas Skotnicki
Sébastien Barnola
Roland Pantel
Claire Fenouillet-Beranger
D. Fleury
Frederic Boeuf
C. Pribat
Pascal Gouraud
C. Laviron
T. Salvetat
Gerard Ghibaudo
L. Clement
P. Perreau
Didier Dutartre
D. Chanemougame
Nicolas Loubet
C. Duluard
Source :
ESSDERC 2008 - 38th European Solid-State Device Research Conference.
Publication Year :
2008
Publisher :
IEEE, 2008.

Abstract

This work proposes a Bulk+ planar fully depleted ldquofoldedrdquo technology as an innovative cost worthy solution for upcoming low power nodes. We report a detailed fabrication method, combining advanced selective epitaxy faceting and SON (Silicon-On-Nothing) process, to provide thin film/thin BOX devices with improved transistor gain beta for a given designed footprint Wdesign. We compare the fabrication between channel, i.e. non-rotated wafer, and channel, i.e. 45deg-rotated wafer, for the same (100) surface orientation.

Details

Database :
OpenAIRE
Journal :
ESSDERC 2008 - 38th European Solid-State Device Research Conference
Accession number :
edsair.doi...........50c5660213f22ab57380f1c522fab8aa