A 1.5-W single-chip MPEG-2 MP@ML video encoder with low power motion estimation and clocking

A 1.5-W single-chip MPEG-2 MP@ML real-time video encoder large scale integrated circuit (LSI) has been developed. To form an MPEG-2 encoder system, we employ two 16-Mb synchronous DRAM's, a microprocessor unit (MPU), and an audio encoder LSI. Owing to a two-step hierarchical search scheme and a novel adaptive search window scheme, the search range of motion estimation is -48/+47 horizontal and -96/+15.5 vertical, and the pseudo search range, which is the size when the location of the search window is adaptively shifted, is -96/+95 horizontal and -32/+31.5 vertical. We have also developed low-power clocking techniques, i.e., demand-clock controller, local-clock controller, and low-power flip-flops, which can eliminate waste of power in clocking. We have successfully fabricated these new designs as a low-power single-chip MPEG-2 encoder LSI. The operating frequency except for a synchronous DRAM interface unit and a video in/out unit is 54 MHz. The supply voltage to the first and second search engines in a motion estimation unit can be successfully lowered to 2.5 V and the others are 3.3 V. Into a 12.45/spl times/12.45 mm/sup 2/ chip with 0.35-/spl mu/m CMOS and triple-metal layer technology are integrated 3.1 M transistors.