Nanoimprint system development for high-volume semiconductor manufacturing the and status of overlay performance

Imprint lithography has been shown to be a promising technique for replication of nano-scale features. Jet and Flash Imprint Lithography* (J-FIL*) involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. There are many criteria that determine whether a particular technology is ready for wafer manufacturing. Included on the list are overlay, throughput and defectivity. The most demanding devices now require overlay of better than 4nm, 3 sigma. Throughput for an imprint tool is generally targeted at 80 wafers per hour. Defectivity and mask life play a significant role relative to meeting the cost of ownership (CoO) requirements in the production of semiconductor devices. The purpose of this paper is to report the status of throughput and defectivity work and to describe the progress made in addressing overlay for advanced devices. In order to address high order corrections, a high order distortion correction (HODC) system is introduced. The combination of applying magnification actuation to the mask, and temperature correction to the wafer is described in detail and examples are presented for the correction of K7, K11 and K17 distortions as well as distortions on actual device wafers.