Analysis of the area efficient transmission gate power clamp in 65nm CMOS process

an area efficient clamp is presented and validated in 65nm low leakage CMOS process. With this novel design, only a very short time constant RC timer is required for triggering and keeping the clamp turning on for shunting the ESD current. And the leakage is greatly reduced in normal operation because of the small capacitor. Robust ESD protection capability and no risk of power on mis-triggering problems are also studied in the paper.