Effects of parasitic capacitance in a magnetically-coupled voltage multiplier

Effects of parasitic capacitance in a magnetically-coupled voltage multiplier (VM) are described. We found that parasitic capacitance between SQUIDs and JTLs in a VM decreases its operating margin. We also found that separation of electric grounds for the output terminal of a VM from those for the JTLs is effective to improve the operating margin. Using this method, a 64-stage VM was fabricated and well-defined output voltage was obtained.