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Segment and Conflict Aware Page Allocation and Migration in DRAM-PCM Hybrid Main Memory
- Source :
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 36:1458-1470
- Publication Year :
- 2017
- Publisher :
- Institute of Electrical and Electronics Engineers (IEEE), 2017.
-
Abstract
- Phase change memory (PCM), given its nonvolatility, potential high density, and low standby power, is a promising candidate to be used as main memory in next generation computer systems. However, to hide its shortcomings of limited endurance and slow write performance, state-of-the-art solutions tend to construct a dynamic RAM (DRAM)-PCM hybrid memory and place write-intensive pages in DRAM. While existing optimizations to this hybrid architecture focus on tuning DRAM configurations to reduce the number of write operations to PCM, this paper explores the interactions between DRAM and PCM to improve both the performance and the endurance of a DRAM-PCM hybrid main memory. Specifically, it exploits the flexibility of mapping virtual pages to physical pages, and develops a proactive strategy to allocate pages taking both program segments and DRAM conflict misses into consideration, thus distributing those heavily written pages across different DRAM sets. Meanwhile, a lifetime-aware DRAM replacement algorithm and a conflict-aware page remapping strategy are proposed to further reduce DRAM misses and PCM writes. Experiments confirm that the proposed techniques are able to improve average memory hit time and reduce maximum PCM write counts thus enhancing both performance and lifetime of a DRAM-PCM hybrid main memory.
- Subjects :
- Computer science
Registered memory
02 engineering and technology
Overlay
01 natural sciences
CAS latency
law.invention
law
Universal memory
0103 physical sciences
0202 electrical engineering, electronic engineering, information engineering
Interleaved memory
Static random-access memory
Electrical and Electronic Engineering
Memory refresh
Computer memory
010302 applied physics
Random access memory
Dynamic random-access memory
Hardware_MEMORYSTRUCTURES
business.industry
Cache-only memory architecture
Uniform memory access
Semiconductor memory
Computer Graphics and Computer-Aided Design
Memory map
Memory controller
020202 computer hardware & architecture
Phase-change memory
Memory management
Demand paging
Embedded system
Virtual memory
Memory rank
business
Software
Dram
Subjects
Details
- ISSN :
- 19374151 and 02780070
- Volume :
- 36
- Database :
- OpenAIRE
- Journal :
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Accession number :
- edsair.doi...........443624ec166f44d5842d77a4ecd6d9f4