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Sequential Element Timing Parameter Definition Considering Clock Uncertainty
- Source :
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 23:2705-2708
- Publication Year :
- 2015
- Publisher :
- Institute of Electrical and Electronics Engineers (IEEE), 2015.
-
Abstract
- When the conventional method of defining sequential element timing parameters is used in conjunction with the conventional method of accounting for clock uncertainty in timing analysis, the results are overly pessimistic because, when clock uncertainty is nonzero, the element can never be simultaneously critical for both setup time and clock-to- $Q$ . This brief shows that the actual sequencing overhead of conventional flip-flops is 0.5–1 fanout-of-4 (FO4) inverter delay shorter than conventional models predict. High-performance flip-flops, with a modest transparency window, can be 2 FO4 delays faster. While the exact overhead becomes a function of the clock uncertainty, for typical uncertainties, the timing parameters are well-approximated using minimum setup and clock-to- $Q$ values.
- Subjects :
- Very-large-scale integration
Synchronous circuit
Computer science
Clock drift
Static timing analysis
Hardware_PERFORMANCEANDRELIABILITY
Digital clock manager
Timing failure
Clock synchronization
Clock angle problem
Hardware and Architecture
Control theory
Clock domain crossing
Electronic engineering
Hardware_ARITHMETICANDLOGICSTRUCTURES
Electrical and Electronic Engineering
Software
Hardware_LOGICDESIGN
Subjects
Details
- ISSN :
- 15579999 and 10638210
- Volume :
- 23
- Database :
- OpenAIRE
- Journal :
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
- Accession number :
- edsair.doi...........3ffc35f44b42420ac5d50b964c77d549