Asynchronous FIFO Design Based on Verilog

With the rapid development of integrated circuits, asynchronous First Input First Output (FIFO) is often used to solve the problem of data transmission across the clock domain. This paper mainly studies the key problem of asynchronous FIFO design - the generation of empty - full signal. To solve this problem, it is necessary to realize the synchronization of signal across the clock domain and convert binary code into gray code to reduce the probability of metastable state. The null and full signals generated by the asynchronous FIFO designed in this paper are false null and false full, but this does not affect the function of the asynchronous FIFO, and will only lose part of the performance. Through Modelsim simulation verification, the designed asynchronous FIFO can realize first-in, first-out of data and correctly generate empty and full signal, which meets the design requirements. The research of this paper is helpful for further application of asynchronous FIFO in data transmission across clock domains.