Parallel quaternary signed-digit arithmetic operations: addition, subtraction, multiplication and division

A quaternary signed-digit number representations-based arithmetic unit is proposed. The arithmetic unit performs parallel one-step addition (subtraction), multiplication and division. We use the symbolic substitution technique to reduce the number of the computation rules involved in the computation rules. Fast parallel nonrecoded quaternary signed-digit multiplication is proposed using our proposed one-step quaternary signed-digit adder. Also, parallel quaternary signed-digit division is performed in constant time by exploiting an iterative conversion algorithm where in every iterative step a negation operation, an addition operation and two multiplication operations are performed. The execution times of the proposed QSD operations are proportional to log2 n, where n are the length of operands.