A Comparative Analysis of Performance Gain of 7 nm FinFET over Planer CMOS

FinFET has been contemplated as a seemly substitute for the conventional CMOS at the nano-scale regime owing to the projection for application in the integrated circuits fabrication due to its extraordinary properties like improved channel controllability, high ON/OFF current ratio and reduced short-channel effect. In this paper, circuit simulations of 7-nm FinFET and planer CMOS are comprehensively investigated showing a 34.92% and 28.79% increased drain current in 7-nm Fin-FET compared to the existing 22-nm and equivalent 7-nm planer CMOS respectively. A detailed simulation study evaluating the performance of the proposed design is presented exhibiting a 2X increase in drive strength with the increment of fins. Fin thickness of 2.725 nm along with a height of 10.9 nm has been used resulting in an 8X reduction in gate area which is the smallest 7-nm Fin-FET structure yet developed. The indiscriminate variations of the characteristics obtained in various simulations lead to a culmination of shifting to Fin-FET from planer CMOS which is imperative from the prospect of design and manufacture. Keywords—FinFET, multi-gate FETs, 7-nm, nanoscale, HSpice