Improved Chain Diagnosis Methodology for Clock and Control Signal Defect Identification

The main goal of existing scan chain diagnosis approaches is to identify a point (or range of points) in the scan chain(s) at which values are directly corrupted due to a defect. A common assumption made in these techniques is the defect causing failure is in the scan chain/path itself. Based on the real silicon failure analysis over years, this assumption is often found to be correct, but not always. Specifically, in cases where a single defect is expected (stress fails and field returns), yet multiple chains fail, this assumption is more often incorrect. In these cases, the defect was found to be in the clock and control signal logic. This paper proposes an improved approach to diagnose defects on clock and control signal lines to enhance accuracy of scan chain diagnosis. Experimental results on injected clock and control signal defects demonstrate the effectiveness of the proposed technique. Physical Failure Analysis (PFA) on selected silicon devices confirmed the results of proposed technique.