FPGA based TDC for the Drift Chamber detector of the KLOE2 experiment

The KLOE2 experiment is operating at the Dafnee e- collider, designed to reach an instantaneous luminosity of 2*10$^{\mathbf {32}} \mathbf {cm} ^{\mathbf {-2}} \mathbf {s} ^{\mathbf {-1}}$ at the $\Phi $ resonance. Secondary vertex displacement are of paramount importance for the measurement of the CP violation in the kaon system. The most relevant detector to identify and reconstrut particles in the final state is the Drift Chamber. After 20 years of operation the front-end electronics of the detector is obsolete. Moreover the drift chamber electronics is based on an ASIC production line which was discontinued. New TDCs (Time to Digital Converter) have to be built whose architecture is based on the newest FPGAs present on the market. In this paper we describe the architecture, the performance of the new TDCs and their FPGA based front-end data acquistition. The new electronics has already been installed in the experiment.