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nZESPA: A Near-3D-Memory Zero Skipping Parallel Accelerator for CNNs

Authors :
Palash Das
Hemangee K. Kapoor
Source :
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 40:1573-1585
Publication Year :
2021
Publisher :
Institute of Electrical and Electronics Engineers (IEEE), 2021.

Abstract

Convolutional neural networks (CNNs) are one of the most popular machine learning tools for computer vision. The ubiquitous use in several applications with its high computation-cost has made it lucrative for optimization through accelerated architecture. State-of-the-art has either exploited the parallelism of CNNs, or eliminated computations through sparsity or used near-memory processing (NMP) to accelerate the CNNs. We introduce NMP-fully sparse architecture, which acquires all three capabilities. The proposed architecture is parallel and hence processes the independent CNN tasks concurrently. To exploit the sparsity, the proposed system employs a dataflow, namely, Near-3D-Memory Zero Skipping Parallel dataflow or nZESPA dataflow. This dataflow maintains the compressed-sparse encoding of data that skips all ineffectual zero-valued computations of CNNs. We design a custom accelerator which employs the nZESPA dataflow. The grids of nZESPA modules are integrated into the logic layer of the hybrid memory cube. This integration saves a significant amount of off-chip communications while implementing the concept of NMP. We compare the proposed architecture with three other architectures which either do not exploit sparsity (NMP-dense) or do not employ NMP (traditional-fully sparse) or do not include both (traditional-dense). The proposed system outperforms the baselines in terms of performance and energy consumption while executing CNN inference.

Details

ISSN :
19374151 and 02780070
Volume :
40
Database :
OpenAIRE
Journal :
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Accession number :
edsair.doi...........374197a6d185aeab4ab62d25a70e1f95
Full Text :
https://doi.org/10.1109/tcad.2020.3022330