Analytic models for crossbar write operation

This paper presents a circuit level analysis of write operation in memristor crossbar memory array with and without line resistance. Three write schemes: floating line, 1/2 and 1/3 are investigated. Analysis shows that floating line scheme could also be considered reliable in arrays with aspect ratio of 1:1 and negligible line resistance just like the latter two schemes. Further analysis also shows that high density crossbar structures cannot be designed using any of the three schemes with worst case line resistance and data distribution within the array. The presented analyses are suitable for modeling the crossbar array as well as evaluating performances during write operation. The output of this work provides the necessary design models that will assist designers in implementation of write techniques in crossbar array in future systems.