An Untrimmed PVT-Robust 12-bit 1-MS/s SAR ADC IP in 55nm Deeply Depleted Channel CMOS Process

This paper presents an industry-ready PVT-robust 12-bit 1 MS/s untrimmed SAR ADC IP operating from 0.5/0.9V supply voltage for a sub-threshold sensor interface. The ADC exploits Fujitsu's 55 nm Deeply Depleted Channel (DDC) technology to dynamically regulate the bulk voltage of the NMOS and PMOS transistors to compensate for the PVT variations. This dynamic regulation of the the bulk voltage is enabled by a technology-assisted replica-biasing based design strategy. This enables a PVT-robust comparator operation up to 14MHz frequency from a 0.5V supply voltage to allow the ADC to achieve 68 $\mathrm{dB}\pm 1.1\mathrm{dB}$ SNDR and 88 $\mathrm{dB}+3.5\mathrm{dB}$ THD over P(SS,TT,FF) - V(0.45V to 0.55V) - T(-40°C to 90°C) variations at an average 12fJ/CS efficiency at $1/10^{th}$ of the sampling frequency.