Fast method for the prediction of the capacitance of via through-holes

Authors :: D. De Zutter
S. Van den Berghe
S. Jegannathan
Source :: IEEE 7th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.98TH8370).
Publication Year :: 2002
Publisher :: IEEE, 2002.
Abstract: In this paper, a fast method for the prediction of the excess capacitance of vias is proposed. The effect of the connecting lines is also examined. Numerical simulations verify the validity of the method proposed. The fast method leads to an upper capacitance bound that is further reduced by the presence of the connecting lines.

Subjects :: Engineering
Printed circuit design
Parasitic capacitance
Differential capacitance
business.industry
Numerical analysis
Hardware_INTEGRATEDCIRCUITS
Electrical engineering
Hardware_PERFORMANCEANDRELIABILITY
Capacitance probe
business
Capacitance

Database :: OpenAIRE
Journal :: IEEE 7th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.98TH8370)
Accession number :: edsair.doi...........303d77a2a03c84f6a599b3e354c6c5a3
Full Text :: https://doi.org/10.1109/epep.1998.733924