Modelling and Fabrication of the Silicon-Based Device Structures for Microelectronic Applications

In this paper the results of micromachining of Si wafer by various approaches are presented. The technological process based on silicon-on-insulator technology (SOI) was developed. It was shown that by choosing the topological size of the grooves, cavities and their shape, it is possible to obtain the cavities underneath the surface of Si wafer. The next procedures of deposition of polysilicon and silicon oxide films allowed to fabricate the sealed SOI cavities, which were considered as the device structures, sensitive or actuator elements. The process of Si-nanostructure fabrication through the wet chemical etching of Si wafer applicable in a wide range of applications is presented.