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A 12.8 GB/S Daisy Chain-Based Downlink I/F Employing Spectrally Compressed Multi-Band Multiplexing for High-Bandwidth and Large-Capacity Storage Systems

Authors :
Jun Deguchi
Takashi Toi
Daisuke Miyashita
Yuta Tsubouchi
Makoto Morimoto
Yuji Satoh
Junii Wadatsumi
Fumihiko Tachibana
Source :
VLSI Circuits
Publication Year :
2018
Publisher :
IEEE, 2018.

Abstract

This paper proposes a prototype downlink I/F employing a tapered-BW daisy-chained topology enabled by a proposed SCM2 technique to exploit the low throughput of NAND I/O, which allows a NAND controller to handle 32 NAND PKGs on a single I/F channel. The fabricated I/F achieved 12.8 Gb/s with BER of 10−12 while consuming 252.1 mW for a TX and 375.7 mW for four RXs. The FoM is 409.6 PKG·Gb/s.

Details

Database :
OpenAIRE
Journal :
2018 IEEE Symposium on VLSI Circuits
Accession number :
edsair.doi...........2c2b38697142eadc86c7275afd407532
Full Text :
https://doi.org/10.1109/vlsic.2018.8502340