A test pattern for three-dimensional latch-up analysis

Authors :: Roberto Menozzi
M. Davoli
Fausto Fantini
I. De Munari
Source :: ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures.
Publication Year :: 2002
Publisher :: IEEE, 2002.
Abstract: By means of both cross-section and layout two-dimensional (2D) numerical simulations, three-dimensional (3D) latch-up interactions are demonstrated to significantly influence the latch-up behavior of a typical CMOS structure. A 3D latch-up test pattern is designed to allow the experimental study of such effects. The first measurement results show complex behaviors that can be overlooked if common 2D test patterns are used. >

Subjects :: CMOS
Computer simulation
Computer science
Electronic engineering
Pattern analysis
Mosfet circuits
Cmos process
Algorithm
Test (assessment)
Shift register

Database :: OpenAIRE
Journal :: ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures
Accession number :: edsair.doi...........2b1fb6dbc3d15f26b09cf525b719677e
Full Text :: https://doi.org/10.1109/icmts.1993.292886