Design Guidelines for Linear Amplification and Low-insertion Loss in 5-GHz-band SOI Power MOSFETs

This paper describes guidelines for designing thinfilm SOI power MOSFETs for linear-amplification and SPDT-switch applications. A fabricated device shows power-added efficiency of 61% at 5.25 GHz (Vdd @ 3.0 V). For linear-amplification, it is important to suppress the parasitic bipolar effect and reduce the on-resistance. For a SPDT-switch, it is important to reduce Ron and use highresistivity Si substrate.