Accuracy-Configurable 2-D Gaussian Filter Architecture for Energy-Efficient Image Processing

Most compute-intensive applications demand approaches to optimize energy efficiency in CMOS design. Configurable architectures and approximate computing are alternatives to meet the quality and energy requirements in multimedia processing during the runtime. This work proposes a 2D Gaussian filter design to provide multiple quality-power-performance points of operation. The main goal is to design an accuracy-configurable 2D Gaussian filter accelerator at the runtime with a low overhead cost when a new configuration is dynamically selected. The power consumption results show reductions ranging from 9.87% to 58.96%, with an up to 14.8% increase in the hardware area.