A 160Gb/s interface design configuration for multichip LSI

Authors :: N. Sasaki
Takayuki Ezaki
H. Yonernura
M. Kitano
S. Tanaka
H. Ozaki
T. Hirayarna
K. Kondo
Source :: 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).
Publication Year :: 2004
Publisher :: IEEE, 2004.
Abstract: The Multichip LSI (MCL) comprised of both an embedded 123MHz CPU and a 64Mb memory in one package is introduced. 1300 signal lines are directly connected by microbumps between the two chips and achieve 160Gb/s signal interface performance. Both the CPU and memory are fabricated in a 0.15/spl mu/m CMOS technology.

Subjects :: S interface
Engineering
CMOS
business.industry
Interface (computing)
Low-power electronics
Hardware_INTEGRATEDCIRCUITS
System on a chip
Central processing unit
Integrated circuit packaging
business
Signal
Computer hardware

Database :: OpenAIRE
Journal :: 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)
Accession number :: edsair.doi...........1d98675372dcf01d21d9ae7ae58322f5
Full Text :: https://doi.org/10.1109/isscc.2004.1332633