Back to Search
Start Over
Utilizing the retiming-skew equivalence in a practical algorithm for retiming large circuits
- Source :
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 15:1237-1248
- Publication Year :
- 1996
- Publisher :
- Institute of Electrical and Electronics Engineers (IEEE), 1996.
-
Abstract
- The introduction of clock skew at an edge-triggered flip-flop has an effect that is similar to the movement of the flip-flop across combinational logic module boundaries, and these are continuous and discrete optimizations with the same effect. While this fact has been recognized before, this paper, for the first time, utilizes this information to find an optimal retiming. The clock period is guaranteed to be at most one gate delay larger than the optimal clock period found using skew alone; note that since skew is a continuous optimization, it is possible that the optimal period may not be achievable. The method views the circuit hierarchically, first solving the clock skew problem at one level above the gate level, and then using local transformations at the gate level to perform retiming for the optimal clock period. The solution is thus divided into two phases. In Phase A, the clock skew optimization problem is solved with the objective of minimizing the clock period, while ensuring that the difference between the maximum and the minimum skew is minimized. Next, in Phase B, retiming is employed and some flip-flops are relocated across gates in an attempt to set the values of all skews to be as close to zero as possible.
- Subjects :
- Skew
Clock gating
Hardware_PERFORMANCEANDRELIABILITY
Digital clock manager
Clock skew
Computer Graphics and Computer-Aided Design
Timing failure
Clock angle problem
Clock domain crossing
Hardware_INTEGRATEDCIRCUITS
Electronic engineering
Hardware_ARITHMETICANDLOGICSTRUCTURES
Electrical and Electronic Engineering
Retiming
Algorithm
Software
Hardware_LOGICDESIGN
Mathematics
Subjects
Details
- ISSN :
- 02780070
- Volume :
- 15
- Database :
- OpenAIRE
- Journal :
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Accession number :
- edsair.doi...........171b7c992c037fb56ae7476052ce61c9