A new patterning process concept for large-area transistor circuit fabrication without using an optical mask aligner

MLA

S. Okazaki, et al. “A New Patterning Process Concept for Large-Area Transistor Circuit Fabrication without Using an Optical Mask Aligner.” IEEE Transactions on Electron Devices, vol. 41, Mar. 1994, pp. 306–14. EBSCOhost, widgets.ebscohost.com/prod/customlink/proxify/proxify.php?count=1&encode=0&proxy=&find_1=&replace_1=&target=https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&scope=site&db=edsair&AN=edsair.doi...........122a1cbea3b8a7bdda78c55c8ad44645&authtype=sso&custid=ns315887.

APA

S. Okazaki, K. Kuwabara, K. Asaka, M. Kobayashi, T. Saito, Y. Mori, Y. Akimoto, Yoshiharu Nagae, H. Matsui, H. Hayama, Kazuyuki Nakamura, E. Kaneko, Hideki Asada, & Yoshiro Mikami. (1994). A new patterning process concept for large-area transistor circuit fabrication without using an optical mask aligner. IEEE Transactions on Electron Devices, 41, 306–314.

Chicago

S. Okazaki, K. Kuwabara, K. Asaka, M. Kobayashi, T. Saito, Y. Mori, Y. Akimoto, et al. 1994. “A New Patterning Process Concept for Large-Area Transistor Circuit Fabrication without Using an Optical Mask Aligner.” IEEE Transactions on Electron Devices 41 (March): 306–14. http://widgets.ebscohost.com/prod/customlink/proxify/proxify.php?count=1&encode=0&proxy=&find_1=&replace_1=&target=https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&scope=site&db=edsair&AN=edsair.doi...........122a1cbea3b8a7bdda78c55c8ad44645&authtype=sso&custid=ns315887.