Symmetric Source and Drain Voltage Clamping Scheme for Complete Source–Drain Symmetry in Field-Effect Transistor Modeling

For structurally symmetric field-effect transistors with respect to the source and the drain, their models should be electrically symmetric about the source–drain interchange. This article shows that the commonly used drain–source voltage clamping technique breaks such a symmetry. This article then presents a symmetric source and drain voltage clamping scheme to solve the problem. The effectiveness of the new scheme is demonstrated by both the planar MOSFET model PSP and the FinFET model BSIM-CMG.