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Technology mapping with all spin logic
- Source :
- DATE
- Publication Year :
- 2017
- Publisher :
- IEEE, 2017.
-
Abstract
- This work is the first to propose a technology mapping algorithm for All Spin Logic (ASL) device. The ASL is the most actively-pursed one among spintronic devices which themselves fall under emerging post-CMOS nano-technologies. We identify the shortcomings of directly applying classical technology mapping with ASL devices, and propose techniques to extend it to handle these shortcomings. Our results show that our ASL-aware technology mapping algorithm can achieve on-average 9.15% and up to 27.27% improvement in delay (when optimizing delay) with slight improvement in area, compared to the solution generated by classical technology mapping. In a broader sense, our results show the need for developing circuit-level CAD tools that are aware of and optimized for emerging nano-technologies in order to better assess their promise as we move to the post-CMOS era.
- Subjects :
- 010302 applied physics
Computer engineering
Spintronics
Computer science
Logic gate
0103 physical sciences
0202 electrical engineering, electronic engineering, information engineering
Electronic engineering
02 engineering and technology
Technology mapping
01 natural sciences
Spin (aerodynamics)
020202 computer hardware & architecture
Subjects
Details
- Database :
- OpenAIRE
- Journal :
- Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017
- Accession number :
- edsair.doi...........0eb2f7da348d152b5379698e9f854143