A 5.8-GHz Frequency Synthesizer with Dynamic Current-Matching Charge Pump Linearization Technique and an Average Varactor Circuit

A 5.8-GHz frequency synthesizer is implemented in TSMC 0.18-μm CMOS process. This paper proposes a dynamic current-matching charge pump linearization technique and uses a current-switching differential Colpitts VCO to lower the phase noise and an averaged varactor circuit to increase the linearity of the VCO tuning range. At the supply voltage of 1.8 V, measured results achieve the locked tuning frequency from 5.55 to 5.94 GHz, corresponding to 6.8 % and the phase noise of −105.83 dBc/Hz at 1 MHz offset frequency from 5.8 GHz. The overall power consumption is 21.6 mW. Including pads, the chip area is 0.729 (0.961 × 0.761) mm2.