Formal Verification of Completion-Completeness for NCL Circuits

Authors :: Sudarshan K. Srinivasan
Scott C. Smith
Son N. Le
Source :: MWSCAS
Publication Year :: 2020
Publisher :: IEEE, 2020.
Abstract: Ensuring completion-completeness is required for delay-insensitivity when utilizing bit-wise completion to pipeline NCL circuits comprised of input-incomplete logic functions. Hence, this work presents an automated formal method to detect NCL circuits that are not completion-complete.

Subjects :: 050101 languages & linguistics
Computer science
Programming language
Pipeline (computing)
05 social sciences
Formal equivalence checking
02 engineering and technology
Formal methods
computer.software_genre
Completeness (logic)
0202 electrical engineering, electronic engineering, information engineering
020201 artificial intelligence & image processing
0501 psychology and cognitive sciences
computer
Formal verification
Hardware_LOGICDESIGN
Electronic circuit

Database :: OpenAIRE
Journal :: 2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS)
Accession number :: edsair.doi...........0d8af13ec8b22a8b0b9387dc87cf3c68
Full Text :: https://doi.org/10.1109/mwscas48704.2020.9184603