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Characterising and modelling shared memory accesses in multiprocessor programs
- Source :
- Parallel Computing. 22:869-893
- Publication Year :
- 1996
- Publisher :
- Elsevier BV, 1996.
-
Abstract
- Directory-based, write-invalidate cache coherence protocols are effective in reducing memory latency in shared memory multiprocessors. However, their performance is highly related to the number of ...
- Subjects :
- Memory coherence
Computer Networks and Communications
CPU cache
Computer science
Cache coloring
Multiprocessing
Parallel computing
Cache pollution
CAS latency
Theoretical Computer Science
Non-uniform memory access
Artificial Intelligence
Write-once
Cache invalidation
Data diffusion machine
Cache algorithms
Distributed shared memory
Snoopy cache
Hardware_MEMORYSTRUCTURES
MESI protocol
Cache-only memory architecture
Uniform memory access
Computer Graphics and Computer-Aided Design
MESIF protocol
Memory map
Shared memory
Computer architecture
Hardware and Architecture
Bus sniffing
Distributed memory
Software
Cache coherence
Subjects
Details
- ISSN :
- 01678191
- Volume :
- 22
- Database :
- OpenAIRE
- Journal :
- Parallel Computing
- Accession number :
- edsair.doi...........0cea8156c2cbd7cb479b9c6851085689
- Full Text :
- https://doi.org/10.1016/0167-8191(96)00025-7