An FPGA Implementation of the Log-MAP Algorithm for a Dirty Paper Coding CODEC

This work describes the log-MAP (BCJR) algorithm implementation of a close to capacity dirty paper coding CODEC. The CODEC consists of eight deep pipeline processors. It decodes blocks of 975 bits in 26.9 ms using less than 9.7% of low-cost FPGA (and no DSP blocks). Two pipelines, for alpha and beta, calculate the values of gamma (of the BCJR) to reduce the storage requirements. The final log-likelihood ratio (LLR) is calculated together with alpha, reusing intermediate results. The number of bits used by the different signals of the processor is easily configurable. It was set to six bits to the channel measure signals and eight bits to log of probability signals like alpha, beta, and others. The CODEC clock was 100 MHz. The achieved bit rate is 36.2 Kbps per CODEC, but multiple CODECs can be fit into a single chip. The CODEC is 3.49 dB from the channel capacity.