Full Scan Structure Application in the Design of 16 Bit MCU

A design project of 16 bit RISC MCU with full scan structure by the tool of SYNOPSYSTM DFT COMPILER. The flip-flops can be linked into the chains; the memory modules in the MCU were tested by the technology of BIST; and the circuits were tested by the test vectors by ATPG. The chip test circuit include 8 chains, and cover rate can reach at 99.20%.