Constant ΔTj Power Cycling Strategy in DC Mode for Top-Metal and Bond-Wire Contacts Degradation Investigations

The study of the impact of junction temperature swings ("Tj) on degradation mechanisms during power cycling tests (PCTs) requires both a control of the applied thermal stress and a separation of degradation modes. The first requirement can be obtained by using a "constant "Tj" power cycling strategy that allows to minimize the cross-interactions between the influencing factors. The second one is made by using a dedicated power module well-suited for targeting only the chips top-side degradations (metallization and bond wire contacts). In this paper, a constant "Tj strategy by gate voltage regulation is performed for power cycling tests in DC-mode. The tested modules are ideally designed for top-metal and bond-wire contacts degradation investigations. From ageing indicator on the collector-emitter voltage (VCE), the results clearly show that three regimes of degradation occur systematically at the IGBT chips top-side, whatever the stress conditions. Moreover, comparative results in 'constant "Tj' and conventional 'constant "I' PCT strategies have shown that the feedback between stresses and damages encountered in the second strategy is more important for low "Tj values than for high "Tj values. In addition, results show that in case of high stresses, the 'constant "Tj' strategy with Vge regulation, gives values close to a 'constant "I' strategy but that the extrapolation towards low values of "Tj can be questionable for the 'constant "Tj' strategy.