622-Mbit/s burst-mode clock and data recovery circuit with duty control in a jitter reduction circuit

A clock and data recovery circuit using the clock jitter reduction technique is proposed for a 622-Mbit/s burst-mode data stream. The clock jitter reduction is achieved by controlling the clock duty cycle with the phase information of the recovered clock. The proposed clock recovery circuit, based on the gated oscillator, recovers a low-jitter output clock with up to 4090 consecutive zeros.