Memory Defect Tolerance Architectures for Nanotechnologies

MLA

Nicolaidis, Michael, et al. “Memory Defect Tolerance Architectures for Nanotechnologies.” Journal of Electronic Testing, vol. 21, no. 4, Aug. 2005, pp. 445–55. EBSCOhost, https://doi.org/10.1007/s10836-005-0971-0.

APA

Nicolaidis, M., Anghel, L., & Achouri, N. (2005). Memory Defect Tolerance Architectures for Nanotechnologies. Journal of Electronic Testing, 21(4), 445–455. https://doi.org/10.1007/s10836-005-0971-0

Chicago

Nicolaidis, Michael, Lorena Anghel, and Nadir Achouri. 2005. “Memory Defect Tolerance Architectures for Nanotechnologies.” Journal of Electronic Testing 21 (4): 445–55. doi:10.1007/s10836-005-0971-0.