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Suppressed Capacitive Coupling in 2 Transistor Gain Cell With Oxide Channel and Split Gate

Authors :
Phadke, Omkar
Gopal Kirtania, Sharadindu
Chakraborty, Dyutimoy
Datta, Suman
Yu, Shimeng
Source :
IEEE Transactions on Electron Devices; November 2024, Vol. 71 Issue: 11 p6749-6755, 7p
Publication Year :
2024

Abstract

In this article, the impact of capacitive coupling in the oxide-channel-based 2 transistor gain cell (2TGC) is evaluated. The study is performed using an experimentally calibrated TCAD model of W-doped In2O3 transistor (IWO MOSFET) in the mixed mode simulation. A write “0,” read “0,” write “1,” read “1” (W0R0W1R1) operation is performed and the storage node (SN) potential is monitored. The SN is capacitively coupled to write and read wordlines (WWL and RWL), which temporarily lowers the SN potential after writing and during a read operation. For an improperly designed 2TGC, capacitive coupling leads to a disturbed read for bit “0,” and reduced sense margin for bit “1.” To mitigate this problem, <inline-formula> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> engineering, appropriate choice of <inline-formula> <tex-math notation="LaTeX">${V}_{\text {HOLD}}$ </tex-math></inline-formula>, and sizing of individual transistors is helpful. To substantially suppress the capacitive coupling, a split gate (SpG) structure design for IWO MOSFET is proposed, which allows for a sizing-independent 2TGC design with an undisturbed read and a higher sense margin than the traditional design.

Details

Language :
English
ISSN :
00189383 and 15579646
Volume :
71
Issue :
11
Database :
Supplemental Index
Journal :
IEEE Transactions on Electron Devices
Publication Type :
Periodical
Accession number :
ejs67817907
Full Text :
https://doi.org/10.1109/TED.2024.3463628