Demonstration of Low Interface Trap Density (~3×1011eV-1cm-2) SiC/SiO2 MOS Capacitor with Excellent Performance Using H2+NO POA Treatment for SiC Power Devices

In this work, we report on the engineering of the SiC/SiO₂ MOS interface using H₂ treatments along with NO POA to improve the interface characteristics and device reliability. Significantly low D_it of 3×10¹¹ eV^-1cm^-2, stable threshold voltage, and long gate oxide lifetime > 10⁵ s have been achieved by H₂ annealing before NO POA of thermal SiO₂. Through device electrical characterization and material analysis, we show that the performance enhancement is due to the reduction of interface defects and trapped charges in the SiO₂ surface layer after the POA treatment, which in turn, significantly suppresses the threshold voltage instability.