Defect Engineering for Enhanced Silicon Radiofrequency Substrates

Herein, high‐resistivity silicon substrates with specific He+ion implantations to mitigate the parasitic surface conduction effect are studied. Several postimplantation thermal annealing conditions are investigated. Substrate performance is assessed at radiofrequencies (RFs) using the small‐signal characterization of coplanar waveguides (CPW) structures. The best effective resistivity (ρeff) of 4 kΩ cm is achieved with the wafer annealed at 600 °C for 2 h. This ρeffvalue is also stable as a function of DC bias applied to the CPWs. Those high RF performances originate from the nature of the defects created by ion implantation. Defects are deeply analyzed using spectroscopy measurement and scanning transmission electron microscopy. Combining these measurements, it is shown that {311} defects are probably responsible for the achieved high RF performances. Finally, the link between charge carriers trapping in the RF domain and defects nature is discussed to develop a defects engineering strategy for low‐loss RF substrates. The proposed fabrication method enables the fabrication of RF passivation layer locally over the wafer, and thus the cointegration of RF devices with fully depleted silicon‐on‐insulator technology. Herein, high‐resistivity silicon substrates with specific He+ion implantations to mitigate the parasitic surface conduction effect are studied. Several postimplantation thermal annealing conditions are investigated. Boasting radiofrequency (RF) performance is obtained for a postimplantation annealing of 600 °C for 2 h. Defects responsible for high RF performance are deeply analyzed using photoluminescence spectroscopy measurement and scanning transmission electron microscopy.