Impact of Interface Trap Charges on Silicon Carbide (4H-SiC) Based Gate – Stack, Dual Metal, Surrounding Gate, FET (4H-SiC- GSDM-SGFET) for Analog and Noise Performance Analysis for 5 G/LTE Applications

This article examines the impact of various interface trap charges on silicon carbide-based gate—stack, dual metal, surrounding gate, FET (4H-SiC-GSDM-SGFET). It has been contrasted for performance with silicon carbide (4H-SiC)-based dual metal, surrounding gate, FET (4H-SiC-DM- SGFET). For both devices, output characteristics including transconductance (gm), output conductance (gd), drain current (Ids), gate capacitance (Cgg), cutoff frequency (fT) and threshold voltage (Vth) have been examined. Surface potential and electron concentration were also inspected using a contour plot for both the device structures. A gate-stack with a high k- dielectric, Lanthanum oxide (La2O3) along with gate dielectric layer Aluminum oxide (Al2O3) was used for proposed structure implementation. Additionally, we investigated how trap charges affect noise figure (NF) and noise conductance (NC). Also, a CMOS inverter has been developed and its output characteristics have been compared for both the device architectures. ATLAS 3-D device simulator has been employed to conduct the simulations.