A 0.68-THz Receiver With Third-Order Subharmonic Mixing in 65-nm CMOS

This article presents a 0.68-THz receiver with the third-order subharmonic mixing in a 65-nm CMOS technology. In this work, a third-order subharmonic mixer based on a double-balanced topology is proposed. The spurious mixing product of the mixer is utilized to increase the IF output of the mixer, thus improving the conversion gain and noise figure of the mixer. Besides, compensating capacitors are incorporated in the double-balanced topology to alleviate the severe signal imbalance in this topology at very high frequencies caused by its layout asymmetry. With enhanced signal balance, the conversion gain, noise figure, and isolation of the third-order subharmonic mixer are improved. The receiver achieves a measured noise figure of 28.4 dB at 682 GHz, including the loss of the antenna. Among all the silicon receivers above 430 GHz, this work has the lowest noise figure. Because of the inherent wide bandwidth of the double-balanced topology, the high order of the subharmonic mixer, and the high multiplying factor of the local oscillator (LO) generation circuits, the proposed receiver with an integrated voltage-controlled oscillator obtains a measured input frequency range of 138 GHz, which is the highest among all the silicon receivers above 400 GHz.