A 200-GHz Power Amplifier With 18.7-dBm Psat in 45-nm CMOS SOI: A Model-Based Large-Signal Approach on Cascaded Series-Connected Power Amplification

This article proposes a novel approach on cascaded series-connected power amplifier (PA) design. High-frequency transistor modeling is employed to analyze the stacked cell, and a methodology is developed to maximize the output power (<inline-formula> <tex-math notation="LaTeX">$P_{\text {out}}$ </tex-math></inline-formula>) and power-added efficiency (PAE) of each cell. The <inline-formula> <tex-math notation="LaTeX">$P_{\text {out}}$ </tex-math></inline-formula> and power gain of the cell are studied, and the optimum operation point is determined. A proof-of-concept integrated PA is implemented in a 45-nm CMOS silicon-on-insulator (SOI) process, where stacking and parallel power combining techniques are adopted to achieve 18.7-dBm <inline-formula> <tex-math notation="LaTeX">$P_{\text {out}}$ </tex-math></inline-formula> and 4.8% PAE at 200 GHz. Each PA unit uses three cascaded gain stages where two-stacked, three-stacked, and five-stacked architectures are employed for the first, second, and third stages, respectively. Four PA units are power-combined by a low-loss 4:1 zero-degree combiner. The amplifier consumes 1.4-W dc power and has a small-signal gain of 14.6 dB at 203.2 GHz. The designed PA occupies <inline-formula> <tex-math notation="LaTeX">$1.28\times 1.05$ </tex-math></inline-formula> mm2 die area, including all pads. To the author’s knowledge, the designed PA achieves the highest <inline-formula> <tex-math notation="LaTeX">$P_{\text {out}}$ </tex-math></inline-formula> and PAE among all the Si counterparts at 200 GHz.