Fully Integrated 3-D Stackable CNTFET/RRAM 1T1R Array as BEOL Buffer Macro for Monolithic 3-D Integration With Analog RRAM-Based Computing-in-Memory

Resistive random access memory (RRAM) has been extensively studied for high-density memory and energy-efficient computing-in-memory (CIM) applications. In this work, for the first time, we present a fully integrated 3-D stackable 1-kb one-CNTFET-one-RRAM (1T1R) array with carbon nanotube (CNT) CMOS peripheral circuits. The 1T1R cells were fabricated with 1024 CNT NFETs and Ta2O5-based multibit RRAMs, while the peripheral circuits consisted of 747 CNT PFETs and 875 NFETs for the word line (WL) 7:128 decoder and 128 drivers. The entire array was fabricated using a low-temperature (<inline-formula> <tex-math notation="LaTeX">$\le 300~^{\circ} \text{C}$ </tex-math></inline-formula>) process, enabling multiple layers of CNTFET/RRAM arrays to be vertically stacked in the backend-of-the-line (BEOL) to boost the integration density and chip functionality. Furthermore, this 1T1R digital memory array was then used as a BEOL buffer macro and monolithically 3-D (M3D) integrated with another 128-kb HfO2-based analog RRAM array and Si CMOS logic to accelerate CIM. The fabricated M3D-CIM chip consisted of three functional layers, whose structural integrity and proper function was validated by extensive structural analysis and electrical measurements. To highlight the advantages of this M3D-CIM architecture, typical neural networks, such as multilayer perceptron (MLP) and ResNET32, were implemented, achieving a GPU-equivalent classification accuracy of up to 96.5% in image classification tasks while consuming <inline-formula> <tex-math notation="LaTeX">$39\times $ </tex-math></inline-formula> less energy. Therefore, this work demonstrates the tremendous potential of the CNT/RRAM-based M3D-CIM architecture for various artificial intelligence (AI) applications.