Impact of High-Level Synthesis on Reliability of Artificial Neural Network Hardware Accelerators

Dedicated hardware is required to efficiently execute the highly resource-demanding modern artificial neural networks (ANNs). The high complexity of ANN systems has motivated the use of high-level synthesis (HLS) tools, which increase design abstraction. Higher abstraction reduces the implementation of field-programmable gate array (FPGA) hardware details visible to the designer, making an accurate reliability evaluation challenging. When ANN hardware accelerators are used in safety-critical systems, reliability becomes paramount, and to have a realistic reliability evaluation, physical fault injection, such as beam testing, is mandatory. Existing reliability analysis approaches focus on specific ANN hardware accelerator designs, but when HLS tools are used, the tool flow and design decisions can impact reliability. Therefore, we evaluate the error rate of ANN hardware accelerators generated by HLS tools under high-energy neutrons and explore the impact of HLS parameters on reliability. Our results show that by tweaking hardware parameters, such as the reuse of resources, it can increase the error rate linearly. Furthermore, the generated ANN hardware accelerator with the best tradeoff of area and execution cycles can deliver <inline-formula> <tex-math notation="LaTeX">$15\times $ </tex-math></inline-formula> more correct executions than the least optimized one, despite its increased error rate.