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Interfacial Layer Selection Methodology for Customized Ferroelectric Memories

Authors :
Lee, Hyun Jae
Moon, Taehwan
Nam, Seunggeol
Bae, Hagyoul
Choe, Duk-Hyun
Jo, Sanghyun
Lee, Yunseong
Park, Yoonsang
Kim, Kihong
Heo, Jinseong
Source :
IEEE Transactions on Electron Devices; 2024, Vol. 71 Issue: 3 p1907-1912, 6p
Publication Year :
2024

Abstract

This study presents a material selection strategy for the interfacial layer (IL) in ferroelectric (FE) memory stacks. The nucleation-limited switching (NLS) model was applied to analyze the switching kinetics of the metal/FE/insulator/metal (MFIM) structure, where Hf0.5Zr0.5O2 (HZO) was used as the FE. Activation field (<inline-formula> <tex-math notation="LaTeX">${E}_{a}$ </tex-math></inline-formula>) and characteristic switching time (<inline-formula> <tex-math notation="LaTeX">$\tau $ </tex-math></inline-formula>) were extracted for various 1-nm-thick ILs, including those of SiO2, La2O3 (LaO), AlN, and Hf3N4 (HfN). The adaptation of HZO/LaO reduced the <inline-formula> <tex-math notation="LaTeX">${E}_{a}$ </tex-math></inline-formula> by ~44% in relation to that of HZO without an IL (MFM-HZO), resulting in considerably faster switching in the low-electric-field (<inline-formula> <tex-math notation="LaTeX">${E}$ </tex-math></inline-formula>) region (< 4 MV<inline-formula> <tex-math notation="LaTeX">$\cdot $ </tex-math></inline-formula>cm<inline-formula> <tex-math notation="LaTeX">$^{-{1}}$ </tex-math></inline-formula>)—a highly suitable criterion for applications in 1-bit nonvolatile memories. In contrast, HZO/AlN showed the broadest <inline-formula> <tex-math notation="LaTeX">$\tau $ </tex-math></inline-formula> distribution due to the large <inline-formula> <tex-math notation="LaTeX">${E}_{a}$ </tex-math></inline-formula> (<inline-formula> <tex-math notation="LaTeX">$\sim $ </tex-math></inline-formula>200% of MFM-HZO), which led to the stabilization of multiple-intermediate polarization states. Promising potentiation and depression characteristics were obtained for multibit synapse applications when an incremental pulse time scheme with a step size of 10 ns was used.

Details

Language :
English
ISSN :
00189383 and 15579646
Volume :
71
Issue :
3
Database :
Supplemental Index
Journal :
IEEE Transactions on Electron Devices
Publication Type :
Periodical
Accession number :
ejs65705082
Full Text :
https://doi.org/10.1109/TED.2024.3360009